This invention relates to a semiconductor memory test system which is capable of testing semiconductor memories by providing address signals and write-in data to the memories under test from a pattern generator, reading out the stored data from the memories under test, and comparing this read-out data with expected data.
FIG. 1 is a block diagram of one example of a conventional semiconductor memory test system 20. According to this system, an address signal is supplied to a memory 13 that is to be tested from an address terminal 12, and data generated by a conventional pattern generator 11 is written-in to this address of the memory 13 via a data terminal 14. After that, the data in the memory 13 is read out to a logic comparator 15, and the readout data is then compared with expected data in the logic comparator 15 to determine whether the memory 13 works correctly or not.
The conventional pattern generator 11 is composed of an address generator 21, a data generator 22, a data memory 23, a clock generator 24, and a sequence control unit 25. The sequence control unit 25 controls the address generator 21, the data generator 22, and the clock generator 24. The address generator 21 generates address signals that are supplied to the memory 13. The data generator 22 generates data to be written into the memory 13 and expected data to be supplied to the logic comparator 15.
Similarly to the data generator 22, the data memory 23 generates write data to be supplied to the memory 13 and the expected data to be outputted to the logic comparator 15. The data generator 22 is utilized for sequential and/or repeatable data generation but the data memory 23 is utilized for irregular or random data generation. A multiplexer 26 selects to output data from the data generator 22 or from the data memory 23 and provides it to the data terminal 14.
In a conventional semiconductor memory test system, such as the one illustrated in FIG. 1, there are several disadvantages, as described below.
(a) One type of memory is capable of inhibiting the writing-in procedure for arbitrary selected bits. In this memory, supplied data is written into the bits which are not inhibited, whereas the previously stored data remains in the bits for which writing-in is inhibited. For testing this type of memory, the expected data must be determined from the combination of data in the memory before write-in, supplied data, and mask data, which determines the inhibited bits. However, since there are many variations of combinations possible, generating the expected data is not possible in a convention memory test system.
(b) For testing a memory which incorporates a logical arithmetic function, expected data must be determined from the supplied data of the pattern generator, the written-in data of the memory under test, and the nature of the arithmetic function in this memory. Therefore, generating the expected data for this type of memory is difficult for a conventional test system.
(c) Another type of memory has both a random access port and a serial access port, as illustrated in FIG. 9. A RAM unit 27 is accessed through the random access port and its operation is identical to dynamic random access memories generally employed. A SAM unit 28 of the memory is accessed by a pointer contained in the memory chip and synchronized by a clock. The pointer is incremented by one as each clock pulse is inputted. Data transfer between the RAM unit 27 and the RAM unit 28 is also possible. The RAM unit 27 functions as a dynamic RAM through the random access port, however, the RAM unit 27 and the SAM unit 28 can also function independently and asynchronously.
For testing the type of memory which has both a random access port and a serial access port as described above, address and data signals have to be provided simultaneously and independently to the RAM unit 27 and the SAM unit 28. Since there is only one set of address and data generators in the conventional pattern generator 11 of a conventional test system, such generation is not possible. Even if the data memory 23 is utilized to generate data, an address from the address generator 21 is needed to access the memory. And if this address is used for the SAM unit 28, it has to be generated in sequential order; thus, address generation for the RAM unit 27, which needs random address generation, is not available.
(d) In a FIFO memory, a write-in address and a read-out address of the FIFO memory having a write-in pointer and a read-out pointer are determined by each pointer, and these pointers are incremented by a write-in clock and a read-out clock respectively. for testing the memory of this kind, the addresses have to be determined by the write-in pointer and the read-out pointer during the write-in and the read-out operations respectively. However, in the conventional memory test system there is only one kind of address generating unit for accessing the data memory 23 for generating the expected data pattern. Therefore, in a conventional test system, it is not possible to generate the address for the read-out pointer while simultaneously generating the address for the write-in pointer.